MyStm32Code/device/Inc/Ramses.h

/*
加入队列 处理
*/
#ifndef __RAMSES__H
#define __RAMSES__H

#ifdef __cplusplus
	extern "C" {
#endif

#include "FreeRTOS.h"
#include "task.h"
#include "main.h"
#include "cmsis_os.h"
#include "usart.h"
 
#include "elog.h"


#include <string.h>
#include "bsp_uart.h"
 

static void Ramses_MAX3160_232(void) 
{
  HAL_GPIO_WritePin(SEL_232_485_GPIO_Port,SEL_232_485_Pin, RESET);
  HAL_GPIO_WritePin(HDPLX_GPIO_Port,HDPLX_Pin, RESET);
}

#define Ramses_CMD_SIZE (8)
#define Ramses_DATA_SIZE (64+8)
#define Ramses_DATA_NUM (8)
#define Ramses_IP_SIZE (16+8)
#define Ramses_INFO_SIZE (8+8)

#define  Ramses_Rcv_Buf_Size   (1024) 
#define  Ramses_Command_Number       2

#define Ramses_FLAG_MASK_BUSY ((uint32_t)1<<(uint32_t)0)
#define Ramses_FLAG_MASK_RECVED_IP ((uint32_t)1<<(uint32_t)1)
#define Ramses_FLAG_MASK_RECVED_DATA ((uint32_t)1<<(uint32_t)2)
#define Ramses_FLAG_MASK_RECVED_INFO ((uint32_t)1<<(uint32_t)3)

typedef int (*Ramses_send_fun)(void *send_class,uint8_t *buf,uint32_t size);

typedef enum 
{
    MODULE_RAMSES_STATE_WAIT,
    MODULE_RAMSES_STATE_TEST,
    MODULE_RAMSES_STATE_TESTING,
    MODULE_RAMSES_STATE_TEST_OK,
    MODULE_RAMSES_STATE_READY,
    MODULE_RAMSES_STATE_START,
    MODULE_RAMSES_STATE_SEND_CMD,
    MODULE_RAMSES_STATE_CHECK_SENSOR,
    MODULE_RAMSES_STATE_GET_DATA,
    MODULE_RAMSES_STATE_OK,
    MODULE_RAMSES_STATE_ERROR,
    MODULE_RAMSES_STATE_STOP
} MODULE_RAMSES_WORK_STATE;

enum trios_integration_time{
    TRIOS_INTEGRATION_TIME_AUTO,
    TRIOS_INTEGRATION_TIME_4MS,
    TRIOS_INTEGRATION_TIME_8MS,
    TRIOS_INTEGRATION_TIME_16MS,
    TRIOS_INTEGRATION_TIME_32MS,
    TRIOS_INTEGRATION_TIME_64MS,
    TRIOS_INTEGRATION_TIME_128MS,
    TRIOS_INTEGRATION_TIME_256MS,
    TRIOS_INTEGRATION_TIME_512MS,
    TRIOS_INTEGRATION_TIME_1024MS,
    TRIOS_INTEGRATION_TIME_2048MS,
    TRIOS_INTEGRATION_TIME_4096MS,
    TRIOS_INTEGRATION_TIME_8192MS
};

typedef struct Ramses_data
{
    uint16_t dev_id;
    uint8_t module_id;
    uint8_t framebyte;
    uint8_t data_size;
    uint8_t *data;
    uint8_t raw[Ramses_DATA_SIZE];
}RAMSES_Data_TypeDef;

typedef struct Ramses_ip
{
    uint16_t dev_id;
    uint8_t module_id;
    uint8_t framebyte;
    uint8_t data_size;
    uint8_t *data;
    uint8_t raw[Ramses_IP_SIZE];
}RAMSES_IP_TypeDef;

typedef struct Ramses_infomation
{
    uint16_t dev_id;
    uint8_t module_id;
    uint16_t serial_number;
    uint8_t firmware_number[2];
    uint8_t individual_information[Ramses_INFO_SIZE-8];
}RAMSES_Info_TypeDef;

typedef enum 
{
  Ramses_Event_Ready ,
  Ramses_Event_Test,
  Ramses_Event_Test_OK  ,
  Ramses_Event_Get_Data,
  Ramses_Event_Check_Data  ,
} Module_Ramses_Event_TypeDef;

// typedef enum 
// {
//   Ramses_State_Waiting  ,
//   Ramses_State_Test ,
//   Ramses_State_Test_Start ,
//   Ramses_State_SN_Getting ,
//   Ramses_State_SN_OK ,
//   Ramses_State_Ready  ,
//   Ramses_State_Get_WAVELENGTH  ,
// //   Ramses_State_Get_WAVELENGTH_Wait  ,
// //   Ramses_State_Get_WAVELENGTH_OK,
// //   Ramses_State_Get_WAVELENGTH_Check  ,
//   Ramses_State_Get_DATA  ,
//   Ramses_State_Get_DATA_Trans,
//   Ramses_State_Get_DATA_Wait  ,
//   Ramses_State_Get_DATA_OK,
//   Ramses_State_Get_DATA_Check  ,
//   Ramses_State_Get_Queue_MSG  ,
//   Ramses_State_Stop ,
//   Ramses_State_Timeout ,
//   Ramses_State_Error   ,
// } Module_Ramses_State_TypeDef;


typedef struct 
{
    int (*init)(void);
    void (*port)(void);
    int (*test)(void);
    void (*start)(void);
    void (*stop)(void);

    osMessageQueueId_t transQueue;  // 队列可选

    volatile MODULE_RAMSES_WORK_STATE state; 
    uint8_t data_ok;                 /* 接收数据完整可以处理 */

    uint8_t result_buf[1024];
    uint16_t size_received;

    volatile uint8_t flag;
    volatile uint8_t flag_ip;
    volatile uint8_t data_index;
    volatile uint8_t recv_buf_p;
    volatile uint8_t data_size;
    volatile uint8_t recv_flag_40;
    uint8_t cmd_buf[Ramses_CMD_SIZE];

    RAMSES_Info_TypeDef information;
    RAMSES_IP_TypeDef ip;
    RAMSES_Data_TypeDef data[Ramses_DATA_NUM];
    uint8_t recv_buf[Ramses_DATA_SIZE];    // 每帧的数据
    uint16_t sn; 
    uint8_t error;

    uint64_t  timebase_ticks;
    uint64_t  timeout_ticks;

}Ramses_TypeDef;

extern UART_HELPER_TypeDef *Ramses_uart_helper;
extern Ramses_TypeDef ramses ;

int Ramses_Init( void );
void Ramses_Port( void);
void Ramses_Task( void *arg);
 
int Ramses_Test(  );
void Ramses_Start(  );
void Ramses_Stop(  );

void Ramses_Set_Sendbuf(   uint8_t * buf, uint16_t size );
void Ramses_Set_Rcvbuf(   uint8_t * buf, uint16_t size );
void Ramses_Set_Timeout_ms(    uint64_t ms_ticks );
int Ramses_Validate(  );


int Ramses_Transmit();
int Ramses_Receive();

void Ramses_Trans_GPIO(void) ;

void Ramses_Trans_Cplt_GPIO(void) ;

int Ramses_CallBack( Ramses_TypeDef *pRamses , uint8_t *buf, uint16_t size );


#ifdef __cplusplus
	}
#endif
#endif


/*
    temp.init();
    temp.port();
    temp.test();

    uint64_t ticks = osKernelGetTickCount();

    while ( temp.state != PH_State_Ready )
    {
        if ( ( osKernelGetTickCount() -ticks) > 3000 )
        {
            log_e(" pH test error.... ") ;
            break;
        }
    }
    log_w(" pH test ok.... ") ;


// osMessageQueueId_t TestQQueueueueHandle;
// osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);
// osMessageQueueGet(TestQueueHandle,osWaitForever);
// osStatus_t osMessageQueueGet ( osMessageQueueId_t  mq_id,
// void *  msg_ptr,       //储存读取结果的变量地址
// uint8_t *  msg_prio,  // ==NULL
// uint32_t  timeout    //阻塞超时时间
// );
// osStatus_t osMessageQueuePut ( osMessageQueueId_t  mq_id,
// const void *  msg_ptr,     //储存写入内容的变量地址
// uint8_t  msg_prio,        //==0U
// uint32_t  timeout         //阻塞超时时间
// );


// uint8_t Ramses_SN_command[8] = {0x01, 0x03, 0x00, 0x0A, 0x00, 0x05, 0xA5, 0xCB};

// uint8_t Ramses_Wavelength_sendbuf[3][8]   = {
//         
//         // 01 03 08 36 00 7A 26 47    (2102  122)
//         // 01 03 08 B0 00 7A C7 AE    (2224  122)
//         // 01 03 09 2A 00 7A E6 7D    (2346  122)
//         
//         { 0x01, 0x03, 0x08, 0x36, 0x00, 0x7A, 0x26, 0x47 },
//         { 0x01, 0x03, 0x08, 0xB0, 0x00, 0x7A, 0xC7, 0xAE },
//         { 0x01, 0x03, 0x09, 0x2A, 0x00, 0x7A, 0xE6, 0x7D }
//     };
// uint8_t Ramses_Data_sendbuf[3][8]   = {
//         
//         //01 03 0A 36 00 7A 27 FF    (2614  122)
//         //01 03 0A B0 00 7A C6 16    (2736  122)
//         //01 03 0B 2A 00 7A E7 C5    (2858  122)
//         
//         { 0x01, 0x03, 0x0A, 0x36, 0x00, 0x7A, 0x27, 0xFF },
//         { 0x01, 0x03, 0x0A, 0xB0, 0x00, 0x7A, 0xC6, 0x16 },
//         { 0x01, 0x03, 0x0B, 0x2A, 0x00, 0x7A, 0xE7, 0xC5 }
//     };
// uint8_t Ramses_sn_buf[15] = {0};


*/